GATE DIELECTRIC BREAKDOWN PHYSICAL ANALYSIS AND STUDIES -2D MODELING OF BREAKDOWN THERMAL EFFECT

Abstract

Ultra thin gate oxide reliability has been an important aspect in the sub-micron fabrication process. Structural deformation at the gate oxide is indeed important to understand the soft breakdown (SBD) and hard breakdown (HBD) mechanisms of a narrow channel MOSFET. During HBD or under favorable condition of SBD, silicon epitaxy growth is observed at the cathode side of the MOSFET. This epitaxy growth is named dielectric breakdown-induced epitaxy (DBIE). DBIE is a likely physical mechanism for the degradation and breakdown of ultra-thin silicon dioxide under constant voltage stress conditions. Therefore, to assure the reliability demands, the physics of the dielectric breakdown-induced epitaxy (DBIE) phenomenon must be fully understood. In this project, a theoretical model has been built based on the electro-thermal migration phenomenon to predict the size of DBIE under the influence of current density and temperature. TEM micrograph observations during the formation of DBIE have been verified by constructing a 2-D transient thermal model using Finite Element Analysis (ANSYS®).