SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS

Abstract

The copper electrodeposition process used for fabricating high aspect ratio throughsilicon via (TSV) structures for three-dimensional integrated circuit (3DIC) application is studied. The kinetics behind the electrodeposition process is analyzed and modeled, accounting for the electrochemistry inherent in the process. The models developed have been used for finite element simulation using the COMSOL Multiphysics software package. The effect of various process and design parameters for electrodeposition such as applied current density (voltage), aspect ratio, tapering angle, pulsing current waveform, etc. on the voiding behavior of the TSV trench and the electrodeposition duration have been comprehensively studied. The novelty of the work lies in the study of very high aspectratio trench structures ranging from 1:15 to 1:20. The parameters of the developed kinetic model were calibrated using past experiments and the simulation results obtained have been used for optimizing the TSV electrodeposition process at the Institute of Microelectronics (IME). The fundamental motivation of this study is to achieve voidfree deposition of TSV trenches at the maximum possible deposition rate so as to maximize the throughput of this process both in the research fab as well as in the industry. The results presented in this study are likely to have a good impact and serve as a useful reference for 3DIC fabrication initiatives in the near future for the microelectronics industry.