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https://scholarbank.nus.edu.sg/handle/10635/153949
| Title: | PROCESS IMPROVEMENT IN 0.152 CMOS FOR PLASMA INDUCED DAMAGE IN GATE CURRENT PERFORMANCE | Authors: | LEE YUN | Keywords: | Plasma induced damage trap charge interface trapped charge gate leakage plasma charging TDDB ILD reliability C-V measurement electron shading effect |
Issue Date: | 2010 | Citation: | LEE YUN (2010). PROCESS IMPROVEMENT IN 0.152 CMOS FOR PLASMA INDUCED DAMAGE IN GATE CURRENT PERFORMANCE. ScholarBank@NUS Repository. | Abstract: | The plasma induced damage has become one of the major issues in current advanced technology. This report seeks to understand the plasma charging effect using different methods to measure the gate current performance. The interface trap density is characterized by Terman's method and high and low frequency C-V method. Based on the hypothesis and comparison of similar technologies, two splits have been carried out. The change of inter layer dielectric (ILD) materials and CVD temperature successfully improves the gate current performance. The time-dependent dielectric breakdown (TDDB) test showed lifetime and reliability of the device. | URI: | https://scholarbank.nus.edu.sg/handle/10635/153949 |
| Appears in Collections: | Master's Theses (Restricted) |
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| File | Description | Size | Format | Access Settings | Version | |
|---|---|---|---|---|---|---|
| Lee Yun.pdf | 4.5 MB | Adobe PDF | RESTRICTED | None | Log In |
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