IMD TDDB (TIME DEPENDENCE DIELECTRIC BREAKDOWN) ON LOW-k DIELETRICS

Abstract

Due to scaling down of microelectronics, many problems are being encountered and one of the problems is RC delay (time response to interconnect). One of the solutions to the RC delay is by replacing Al with a lower resistance material such as Cu and also by using low-k dielectrics. Nevertheless, this solution is still facing problems due to copper's electro-migration and stress migration, as well as low-k dielectrics' weak thermo-mechanical properties. Moreover, it is exacerbated by interconnect scaling, whereby electric field experienced by the intra-metal dielectric increases and line edge roughness becomes significant (process variation of center and edge). Due to process variation, wafer's edge generally has smaller spacing (higher electric field) than the center's one. This fact gives problems in measuring time to break down (TDDB) while applying homogenous voltage stress to such non-homogenous wafer. This project was done in order to provide light in solving the problems by idea of "life time projection based on equal E-field". By considering each die's spacing and applying required voltage stress for each die, the equal electrical field is expected to be applied to whole wafer. Indeed, results shown that by implementing this new method, the higher beta reliability of TDDB testing is obtained compared with the old method, which applies homogenous voltage for all dies.