Communication-aware face detection using noc architecture

Abstract

Face detection is an essential first step towards many advanced computer vision, biometrics recognition and multimedia applications, such as face tracking, face recognition, and video surveillance. In this paper, we proposed an FPGA hardware design with NoC (Network-on-Chip) architecture based on an AdaBoost face detection algorithm. The AdaBoost-based method is the state-of-the-art face detection algorithm in terms of speed and detection rates and the NoC provides high communication capability architecture. This design is verified on a Xilinx Virtex-II Pro FPGA platform. Simulation results show the improvement in speed 40 frames per second compared to software implementation. The NoC architecture provides scalability so that our proposed face detection method can be sped up by adding multiple classifier modules.