A note on compiling FORTRAN loop kernels onto a dataflow architecture

Abstract

Currently, dataflow architectures are programmed using applicative languages to ease the task of deriving the dataflow graph during compilation. We summarise our experience gained in prototyping a FORTRAN nested loop kernel compiler for a pipeline-ring dataflow architecture. We present the status of the current implementation and future directions which the development of the compiler will take. Current evidence suggests that it is possible to efficiently compile FORTRAN nested loop kernels directly onto dataflow architectures without the need for additional run-time support mechanisms. We present a scheme for deriving the dataflow graph from the analysis of "carried" array variable subscript expressions, and a scheme to map the actors in the dataflow graph onto a pipeline-ring of Field Programmable Gate Array (FPGA) devices.