Fast Vth instability in HfO2 gate dielectric MOSFETs and Its impact on digital circuits

Abstract

Fast component of Vth instability in MOSFET with HfO2 gate dielectric is systematically measured and characterized. A charge trapping/detrapping model is used to simulate the Vth instability with overall agreement with the experiments. Experimental and modeling data provide and predict the fast Vth shift under both static and dynamic stress conditions. These data are incorporated into HSpice circuit simulation to evaluate the impact of Vth shift on the performance of digital circuit in realistic situations. Considering the properties of the fast V th instability, circuit performance can be optimized by circuit design in addition to process improvements. This should be included to the guideline of process development and circuit design for future CMOSFET digital systems. © 2006 IEEE.