Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/113241
DC FieldValue
dc.titlePerformance improvement of a genetic algorithm for floorplanning with parallel computing technology
dc.contributor.authorFoo, Han Yang
dc.contributor.authorEsbensen, Henrik
dc.contributor.authorSong, Jianjian
dc.contributor.authorZhuang, Wenjun
dc.contributor.authorKuh, Ernest S.
dc.date.accessioned2014-11-30T06:41:18Z
dc.date.available2014-11-30T06:41:18Z
dc.date.issued1997
dc.identifier.citationFoo, Han Yang,Esbensen, Henrik,Song, Jianjian,Zhuang, Wenjun,Kuh, Ernest S. (1997). Performance improvement of a genetic algorithm for floorplanning with parallel computing technology. Proceedings - IEEE International Symposium on Circuits and Systems 3 : 1544-1547. ScholarBank@NUS Repository.
dc.identifier.issn02714310
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/113241
dc.description.abstractThis paper presents a parallel implementation of a genetic algorithm for floorplanning. It discusses the strategy and implementation and proposes a Multi-Selection-Multi-Evolution (MSME) parallelization scheme. The initial experimental results on a 12-node IBM SP2 scalable parallel computer have shown that the scheme is effective in improving performance of floorplanning over that of a serial implementation. The parallel version could obtain better results with more than 80% of probability and the improvements on chip area and maximum path delay could be more than 20% in the best cases.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentNATIONAL SUPERCOMPUTING RESEARCH CENTRE
dc.description.sourcetitleProceedings - IEEE International Symposium on Circuits and Systems
dc.description.volume3
dc.description.page1544-1547
dc.description.codenPICSD
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Staff Publications

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