Please use this identifier to cite or link to this item:
|Title:||Design of the DUPLEX machine|
|Authors:||Loh, Wai Lung|
|Source:||Loh, Wai Lung (1995). Design of the DUPLEX machine. IEEE Region 10's Annual International Conference, Proceedings 2 : 718-722. ScholarBank@NUS Repository.|
|Abstract:||As computers become less expensive, interest in using CPUs to build novel parallel systems has increased. The goal is to achieve high parallelism at low cost. In this article, we first examine the reasons why we need graph reduction machine for the support of declarative languages to achieve high parallelism. The next is to survey recent development in graph reduction machines, to point out their strengths and weaknesses. Then we introduce a dual unit processing node architecture for the graph reduction machine that carefully separates the work load, as such one unit is responsible for network message handling and the other for supercombinator execution. Finally, we demonstrate that a highly parallel novel computer architecture is feasible at low cost.|
|Source Title:||IEEE Region 10's Annual International Conference, Proceedings|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Feb 16, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.