Please use this identifier to cite or link to this item: https://doi.org/10.1109/TEPM.2008.2004500
Title: Bed of nails - 100-μm-pitch wafer-level interconnections process
Authors: Vempati, S.R.
Tay, A.A.O. 
Kripesh, V.
Yoon, S.W.
Keywords: Failure analysis
Packaging
Photolithography
Reliability
Issue Date: 2008
Source: Vempati, S.R., Tay, A.A.O., Kripesh, V., Yoon, S.W. (2008). Bed of nails - 100-μm-pitch wafer-level interconnections process. IEEE Transactions on Electronics Packaging Manufacturing 31 (4) : 333-340. ScholarBank@NUS Repository. https://doi.org/10.1109/TEPM.2008.2004500
Abstract: The rapid advances in integrated chip (IC) design and fabrication continue to challenge electronic packaging technology, in terms of fine pitch, high performance, low cost, and reliability. Demand for higher input/output (I/O) count per IC chip increases as the IC chip fabrication technology is continuously moving towards nano ICs with feature size less than 90 nm. As micro systems continue to move towards high speed and microminiaturization technologies, stringent electrical and mechanical properties are required. To meet the above requirements, chip-to-substrate interconnection technologies with less than 100-μm pitch are required. Currently, the coefficient of thermal expansion (CTE) mismatch between the Si chip and the substrate serves as the biggest bottleneck issue in conventional chip to substrate interconnections technology, which becomes even more critical as the pitch of the interconnects is reduces. Further, the assembly yield of such fine-pitch interconnections also serves as one of the biggest challenges. Bed-of-nails (BoN) interconnects show great potential in meeting some of these requirements for next-generation packaging. In the present study, BoN interconnects prepared by a novel process called copper column wafer-level packaging is presented. The BoN interconnect technology is being developed to meet fine pitch of 100 μm and high-density interconnections. These BoN interconnects are demonstrated by designing a test chip of 10 × 10 mm2 size with 3338 I/Os and fabricated using an optimized process. The board-level reliability tests performed under temperature cycling in the range of -40 °C to 125 °C show promising results. © 2008 IEEE.
Source Title: IEEE Transactions on Electronics Packaging Manufacturing
URI: http://scholarbank.nus.edu.sg/handle/10635/84883
ISSN: 1521334X
DOI: 10.1109/TEPM.2008.2004500
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