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Title: Si-nanowire TAHOS TaN/AI2O3/HfO2/SiO 2/Si nonvolatile memory cell
Authors: Fu, J.
Singh, N.
Yang, B.
Zhu, C.X. 
Lo, G.Q.
Kwong, D.L.
Issue Date: 2008
Citation: Fu, J., Singh, N., Yang, B., Zhu, C.X., Lo, G.Q., Kwong, D.L. (2008). Si-nanowire TAHOS TaN/AI2O3/HfO2/SiO 2/Si nonvolatile memory cell. ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference : 115-118. ScholarBank@NUS Repository.
Abstract: Silicon nanowire based discrete trapped charge-storage nonvolatile memory cell employing high-K dielectrics with metal gate is presented for the first time. The nanowire TAHOS (TaN/Al2O3HfO2SiO 2Si) memory fabricated using top-down method in nearly gate-all-around (GAA) architecture showed higher P/E speed than SONOS. In TAHOS, the erase speed is found almost equal to the program speed. The improvements are attributed to the reduced electrical oxide thickness (EOT) of the dielectric layers, increased electric field in tunnel oxide, deep trap levels in the Hf02 charge trapping layer, and suppression of gate electron injection by A12O3 blocking layer. The fabricated nanowire TAHOS devices also exhibit large window after ten year of retention, achieving a better trade-off between long retention and fast program/erase property. © 2008 IEEE.
Source Title: ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference
ISBN: 9781424423644
DOI: 10.1109/ESSDERC.2008.4681712
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