Please use this identifier to cite or link to this item: https://doi.org/10.1109/VTSA.2008.4530830
Title: Realization of silicon-germanium-tin (SiGeSn) source/ drain stressors by Sn implant and solid phase epitaxy for strain engineering in SiGe channel P-MOSFETs
Authors: Wang, G.H.
Toh, E.-H.
Chan, T.K.
Osipowicz, T.
Foo, Y.-L.
Tung, C.H.
Lo, G.-Q.
Samudra, G. 
Yeo, Y.-C. 
Issue Date: 2008
Citation: Wang, G.H., Toh, E.-H., Chan, T.K., Osipowicz, T., Foo, Y.-L., Tung, C.H., Lo, G.-Q., Samudra, G., Yeo, Y.-C. (2008). Realization of silicon-germanium-tin (SiGeSn) source/ drain stressors by Sn implant and solid phase epitaxy for strain engineering in SiGe channel P-MOSFETs. International Symposium on VLSI Technology, Systems, and Applications, Proceedings : 128-129. ScholarBank@NUS Repository. https://doi.org/10.1109/VTSA.2008.4530830
Abstract: We report the first demonstration of silicon-gerrnanium-tin (SiGeSn) source and drain (S/D) stressors formed by Sn implant and solid-phase epitaxy (SPE). SPE was developed to achieve high levels of Sn substitutionality in SiGe S/D, to induce compressive strain in the channel. No recess etch or epi deposition steps were required, leading to minimal incremental process cost. SiGeSn S/D can be easily integrated in a standard CMOS process. Sub-50 nm p-FETs were fabricated. With a substitutional Sn concentration of 6.6% in SiGe S/D, having an equivalent lattice constant to that of Si0.4GC0.6, enhancement of IDsat and bole mobility (μhole) are 48% and 88% respectively, over p-FETs without Sn implant. With the demonstration of SiGeSn S/D stressors, we provide a technology extension to SiGe S/D technology for further p-FET enhancement. © 2008 IEEE.
Source Title: International Symposium on VLSI Technology, Systems, and Applications, Proceedings
URI: http://scholarbank.nus.edu.sg/handle/10635/84127
ISBN: 9781424416158
DOI: 10.1109/VTSA.2008.4530830
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