Please use this identifier to cite or link to this item: https://doi.org/10.1109/CASES.2013.6662505
Title: Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems
Authors: Das, A.
Kumar, A. 
Veeravalli, B. 
Issue Date: 2013
Citation: Das, A.,Kumar, A.,Veeravalli, B. (2013). Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems. 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013 : -. ScholarBank@NUS Repository. https://doi.org/10.1109/CASES.2013.6662505
Abstract: Homogeneous multiprocessor systems with reconfigurable area (also known as Reconfigurable Multiprocessor Systems) are emerging as a popular design choice in current and future technology nodes to meet the heterogeneous computing demand of a multitude of applications enabled on these platforms. Application specific mapping decisions on such a platform involve partitioning a given application into software tasks (executed on one or more of the general purpose processors, GPPs) and the hardware tasks (realized as dedicated hardware on the reconfigurable area) to optimize and/or satisfy design constraints such as reliability, performance and design cost. Improving the reliability considering transient faults by increasing the number of checkpoints negatively impacts the reliability considering permanent faults. This trade-off is ignored in all prior studies on task mapping and scheduling. This paper proposes an optimization technique to decide the optimal number of checkpoints for the software tasks which minimizes aging of the GPPs while maximizing the transient fault-tolerance of the overall platform (GPPs and the reconfigurable area) and satisfying design cost and performance. Experiments conducted with synthetic and real-life application task graphs (cyclic and acyclic) demonstrate that the proposed technique minimizes aging and improves the platform lifetime by an average 60% as compared to the existing transient fault-aware techniques. Further, a gradient-based heuristic is proposed to minimize the design space exploration time by upto 500× with less than 5% deviation from optimal solution. © 2013 IEEE.
Source Title: 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013
URI: http://scholarbank.nus.edu.sg/handle/10635/83448
DOI: 10.1109/CASES.2013.6662505
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