Please use this identifier to cite or link to this item: https://doi.org/10.1109/66.999586
Title: Supply-voltage optimization for below-70-nm technology-node MOSFETs
Authors: Wakabayashi, H.
Samudra, G.S. 
Djomehri, I.J.
Nayfeh, H.
Antoniadis, D.A.
Keywords: CMOS
Energy-delay product
Gate delay
Power consumption
Power-supply voltage
Short-channel effect
Issue Date: May-2002
Citation: Wakabayashi, H., Samudra, G.S., Djomehri, I.J., Nayfeh, H., Antoniadis, D.A. (2002-05). Supply-voltage optimization for below-70-nm technology-node MOSFETs. IEEE Transactions on Semiconductor Manufacturing 15 (2) : 151-156. ScholarBank@NUS Repository. https://doi.org/10.1109/66.999586
Abstract: A tradeoff between the performance and power consumption is discussed for below-70-nm technology-node MOSFETs, as a function of power-supply voltage. In order to optimize the supply voltage, gate-delay (CV/I)and energy-delay product (C 2V 3/I) trends are evaluated using the characteristics of down to 24-nm physical-gate-length nMOSFETs. The gate-delay dependence on the supply voltage down to 0.9 V is almost constant at the same OFF current of 100 nA/μm. On the other hand, an optimum supply voltage for the energy-delay product significantly depends on the short-channel characteristics, and is interpreted with analytic expressions. Therefore, for the below-70-nm technology node at sub-1.0 V, it is important to design the power-supply voltage taking into consideration of a short-channel effect (SCE).
Source Title: IEEE Transactions on Semiconductor Manufacturing
URI: http://scholarbank.nus.edu.sg/handle/10635/83117
ISSN: 08946507
DOI: 10.1109/66.999586
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