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|Title:||Chip-level thermoelectric power generators based on high-density silicon nanowire array prepared with top-down CMOS technology|
|Citation:||Li, Y., Buddharaju, K., Singh, N., Lo, G.Q., Lee, S.J. (2011-05). Chip-level thermoelectric power generators based on high-density silicon nanowire array prepared with top-down CMOS technology. IEEE Electron Device Letters 32 (5) : 674-676. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2011.2114634|
|Abstract:||This letter, for the first time, reports a high-density silicon-nanowire (SiNW)-based thermoelectric generator (TEG) prepared by a top-down CMOS-compatible technique. The 5 mm × 5 mm TEG comprises of densely packed alternating n- and p-type SiNW bundles with each wire having a diameter of 80 nm and a height of 1 μm. Each bundle serving as an individual thermoelectric element, having 540 × 540 wires, was connected electrically in series and thermally in parallel. The fabricated TEG demonstrates thermoelectric power generation with an open circuit voltage (Voc) of 1.5 mV and a short circuit current (Isc) of 3.79 μA with an estimated temperature gradient across the device of 0.12 K. © 2011 IEEE.|
|Source Title:||IEEE Electron Device Letters|
|Appears in Collections:||Staff Publications|
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