Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2009.2015588
Title: Characterization and modeling of subfemtofarad nanowire capacitance using the CBCM technique
Authors: Zhao, H.
Kim, R.
Paul, A.
Luisier, M.
Klimeck, G.
Ma, F.-J. 
Rustagi, S.C.
Samudra, G.S. 
Singh, N.
Lo, G.-Q.
Kwong, D.-L.
Keywords: Charge-based capacitance measurement (CBCM)
Nanowire MOSFETs
Self-consistent C-V modeling
Subfemtofarad-capacitance measurement
Issue Date: 2009
Citation: Zhao, H., Kim, R., Paul, A., Luisier, M., Klimeck, G., Ma, F.-J., Rustagi, S.C., Samudra, G.S., Singh, N., Lo, G.-Q., Kwong, D.-L. (2009). Characterization and modeling of subfemtofarad nanowire capacitance using the CBCM technique. IEEE Electron Device Letters 30 (5) : 526-528. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2009.2015588
Abstract: The experimental characterization of gate capacitance in nanoscale devices is challenging. We report an application of the charge-based capacitance measurement (CBCM) technique to measure the gate capacitance of a single-channel nanowire transistor. The measurement results are validated by 3-D electrostatic computations for parasitic estimation and 2-D self-consistent sp3s*d5 tight-binding computations for intrinsic gate capacitance calculations. The device simulation domains were constructed based on SEM and TEM images of the experimental device. The carefully designed CBCM technique thus emerges as a useful technique for measuring the capacitance and characterizing the transport in nanoscale devices. © 2009 IEEE.
Source Title: IEEE Electron Device Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/82038
ISSN: 07413106
DOI: 10.1109/LED.2009.2015588
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