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Title: Characteristics of self-aligned gate-first Ge p- and n-channel MOSFETs using CVD HfO2 gate dielectric and Si surface passivation
Authors: Wu, N.
Zhang, Q.
Balasubramanian, N.
Chan, D.S.H. 
Zhu, C. 
Keywords: Bias temperature instability (BTI)
Charge trapping
High-κ gate dielectrics
Issue Date: Apr-2007
Citation: Wu, N., Zhang, Q., Balasubramanian, N., Chan, D.S.H., Zhu, C. (2007-04). Characteristics of self-aligned gate-first Ge p- and n-channel MOSFETs using CVD HfO2 gate dielectric and Si surface passivation. IEEE Transactions on Electron Devices 54 (4) : 733-741. ScholarBank@NUS Repository.
Abstract: The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO2 as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-κ deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO2 gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO2/Si system at high electric field (∼0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO2/Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication. © 2007 IEEE.
Source Title: IEEE Transactions on Electron Devices
ISSN: 00189383
DOI: 10.1109/TED.2007.892358
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