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|Title:||Border-trap characterization in high-κ strained-Si MOSFETs|
|Citation:||Maji, D., Duttagupta, S.P., Rao, V.R., Yeo, C.C., Cho, B.-J. (2007-08). Border-trap characterization in high-κ strained-Si MOSFETs. IEEE Electron Device Letters 28 (8) : 731-733. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2007.902086|
|Abstract:||In this letter, we focus on the border-trap characterization of TaN/ HfO2/Si and TaN/HfO2/strained-Si/Si0.8 Ge0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-κ films on strained-Si/ Si0.8Ge0.2. These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-κ films on strained-Si are also proposed. © 2007 IEEE.|
|Source Title:||IEEE Electron Device Letters|
|Appears in Collections:||Staff Publications|
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