Please use this identifier to cite or link to this item:
|Title:||A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance|
Impact-ionization MOS (I-MOS)
|Citation:||Toh, E.-H., Wang, G.H., Chan, L., Samudra, G., Yeo, Y.-C. (2008-02). A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance. IEEE Electron Device Letters 29 (2) : 189-191. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2007.914100|
|Abstract:||In this letter, a double-spacer (DS) design is utilized for the formation of shallow source and lightly doped drain to further optimize the impact-ionization MOS (I-MOS) transistor structure. The breakdown voltage VBD needed for avalanche breakdown is lowered due to the shallow source extension. With the formation of the lightly doped drain extension, the impact of drain bias on breakdown voltage, and hence, the threshold voltage VT is also reduced. The DS I-MOS is fabricated and characterized. Detailed analysis and physical explanation of the impact of drain/gate bias on the device characteristics are provided. Compared to the conventional I-MOS transistor, the shallow source extension reduces the breakdown voltage [drain-induced breakdown voltage lowering (DIBVL)] by 0.3-0.6 V, and the lightly doped drain extension reduces the DIBVL up to 0.17 V/V. In addition, excellent subthreshold swing and good device performance are achieved. © 2008 IEEE.|
|Source Title:||IEEE Electron Device Letters|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Jan 11, 2019
WEB OF SCIENCETM
checked on Jan 2, 2019
checked on Dec 28, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.