New partial SOI LDMOS device with high power-added efficiency for 2 GHz RF power amplifier applications

Abstract

For cellular applications, it is an important concern to raise the power-added efficiency of the RF power amplifier. For this, a lower output capacitance for a transistor device is of vital factor to obtain a higher efficiency. In order to improve the LDMOS output properties, a new partial SOI RF LDMOS structure is proposed in this paper. The partial SOI structure is built on an ordinary bulk wafer to avoid the high cost of using an SOI starting wafer. By optimising the transistor structure, a 57% reduction of the output capacitance and a 37% output power increase were obtained by MEDICI simulations. Besides, the oxide layer underneath the drain emitter can divert some crowded electric field. Therefore for devices with same blocking voltage capability, the proposed structure uses a thinner Epi-layer. This decreases the thickness of p+ sinker junction as well as the device. These properties prove to be of great advantage in RF power amplification applications, as it would maximise power added efficiency (PAE) and integration abilities. Laboratory measurements on the fabricated samples showed that more than 50% reduction in Cds can be achieved.