Plasma etching optimization of oxide/nitride/oxide interpoly dielectric breakdown time in flash memory devices

Please use this identifier to cite or link to this item: https://doi.org/10.1109/66.857949

Title:	Plasma etching optimization of oxide/nitride/oxide interpoly dielectric breakdown time in flash memory devices
Authors:	Cha, C.L. Chor, E.F. Gong, H. Zhang, A.Q. Chan, L.
Keywords:	Breakdown time Flash memory devices Interpoly dielectric Optimization Plasma etching
Issue Date:	2000
Citation:	Cha, C.L.,Chor, E.F.,Gong, H.,Zhang, A.Q.,Chan, L. (2000). Plasma etching optimization of oxide/nitride/oxide interpoly dielectric breakdown time in flash memory devices. IEEE Transactions on Semiconductor Manufacturing 13 (3) : 386-389. ScholarBank@NUS Repository. https://doi.org/10.1109/66.857949
Abstract:	The breakdown time of flash memory oxide/nitride/oxide (ONO) layer tbd under positive constant current stressing has been found to be closely related to the cumulative extent of (over)etch of the tungsten silicide, control polysilicon, and ONO layers, i.e., Σ(ΛOE). An empirical first-order relation between tbd and Σ(ΛOE) has been derived to facilitate the plasma etch recipe optimization. This has led to a four-fold increase in the average tbd across a 200-mm wafer to 208 s. More importantly, the spread in tbd has been tightened to ∼5%, which is down from ∼54%. © 2000 IEEE.
Source Title:	IEEE Transactions on Semiconductor Manufacturing
URI:	http://scholarbank.nus.edu.sg/handle/10635/80991
ISSN:	08946507
DOI:	10.1109/66.857949
Appears in Collections:	Staff Publications

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