Parallel and pipelined implementations of injected numerator lattice digital filters

Abstract

Parallel and pipelined implementations are effective measures for improving the maximum permissible sampling rate of a digital filter if all the data required by the arithmetic units are immediately available on demand. This implies that parallel access to the data should be possible and that for any loop in the signal flow graph the total number of series delay elements should be at least equal to the total number of pipelined stages in that loop. In the conventional lattice form IIR digital filter, the feedback loops are single-delay loops. As a consequence, the conventional lattice form IIR filter does not benefit significantly from parallel and pipelined implementation scheme. In this paper, we introduce a new lattice form IIR filter structure where the number of delay elements in the loops can be set arbitrarily. This renders the new lattice form IIR filter amenable to parallel and pipelined implementation.