Novel voltage-tunable, low-voltage linear CMOS transconductor

Please use this identifier to cite or link to this item: https://doi.org/10.1023/A:1008379905128

Title:	Novel voltage-tunable, low-voltage linear CMOS transconductor
Authors:	Lai, W.H. Zhang, X.W. Li, M.-F.
Issue Date:	Jul-2000
Citation:	Lai, W.H., Zhang, X.W., Li, M.-F. (2000-07). Novel voltage-tunable, low-voltage linear CMOS transconductor. Analog Integrated Circuits and Signal Processing 24 (2) : 123-128. ScholarBank@NUS Repository. https://doi.org/10.1023/A:1008379905128
Abstract:	A novel voltage-tunable, low-voltage linear CMOS transconductor design is described. The design is based on the improvement of the cross-coupled pairs. SPICE simulation results show that using BSIM models, MOSIS 2-μm n-well process parameters and a power supply of ± 2.5 V, the linearity error is less than 0.4% over a differential input voltage range of ± 1.2 V. The THD for a differential input voltage of 1 Vpp at 1 kHz is 1.3%.
Source Title:	Analog Integrated Circuits and Signal Processing
URI:	http://scholarbank.nus.edu.sg/handle/10635/80841
ISSN:	09251030
DOI:	10.1023/A:1008379905128
Appears in Collections:	Staff Publications

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