LOW POWER CIRCUITS DESIGN USING RESISTIVE NON-VOLATILE MEMORIES

Abstract

The increasing leakage current in the complementary metal oxide semiconductor (CMOS) circuits due to technology nodes scaling down has been one of the critical issues in the current generation digital circuits and field programmable gate arrays (FPGAs). There are growing research effort in the integration of resistive non-volatile memory (NVM) cells to achieve low power high performance circuits. Although the reported circuits help to minimize the sleep power consumption of the system, there are various drawbacks that limit the performance or reliability of the circuits. This dissertation presents new schemes for both digital circuits and FPGAs to achieve low power and high performance circuits. The new non-volatile flip-flops (nvFFs) and localized NVM array based on spin transfer torque MRAM (STT-MRAM) are proposed to retain the states of registers during standby. Both designs are targeting for the low VDD and low write power. The nvFF can be designed as a standard cell to be compatible with digital design flow thus the design cycle could be greatly reduced. The localized NVM array could further reduce the power consumption with higher density. The non-volatile storage elements proposed for the non-volatile FPGAs (nvFPGAs) are targeting for the high reliability, high density and low power. Compared to the conventional nvFPGAs, the reliability is significantly improved and power is greatly reduced, while compared to the static random access memory (SRAM) based FPGAs, the FPGA area and power could be greatly reduced.