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|Title:||Effect of wafer level packaging, silicon substrate and board material on gigabit board-silicon-board data transmission|
|Source:||Kim, W.,Madhavan, R.,Mao, J.,Choi, J.,Choi, S.,Ravi, D.,Sundaram, V.,Sankararaman, S.,Gupta, P.,Zhang, Z.,Lo, G.,Swaminathan, M.,Tummala, R.,Sitaraman, S.,Wong, C.P.,Iyer, M.,Rotaru, M.,Tay, A. (2004). Effect of wafer level packaging, silicon substrate and board material on gigabit board-silicon-board data transmission. Proceedings - Electronic Components and Technology Conference 2 : 1506-1512. ScholarBank@NUS Repository.|
|Abstract:||This paper discusses the effect of wafer level packaging, silicon substrate, and board material on gigabit data transmission. A test vehicle consisting of a co-planar silicon transmission line, two board transmission lines and wafer level packaging was used for evaluation. A silicon substrate with 100 Ω-cm resistivity was compared with a silicon substrate with 2000 Ω-cm resistivity to investigate the effect of silicon substrate on gigabit data transmission. For board transmission lines, six board materials such as Ciba thin film, Vialux from Dupont, FR4, Hitachi MCL-LX67, Nelco N4000-12, and APPE were compared to investigate the effect of board material. For wafer-level packaging, solder bumps with 50um diameter and 100um pitch were used, and the effect of parasitic capacitance in the solder bumps on gigabit data transmission was investigated. For the accurate simulation of the test vehicle in the time domain, a TDR characterization method and non-physical RLGC models for lossy transmission lines were used to characterize board and silicon transmission lines. This paper shows that better signal integrity in the test vehicle cannot be achieved only by using lower loss material, but also requires low parasitic capacitance for gigabit data transmission.|
|Source Title:||Proceedings - Electronic Components and Technology Conference|
|Appears in Collections:||Staff Publications|
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