Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/72523
Title: Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements
Authors: Kok, C.K.
Chew, W.C.
Chim, W.K. 
Chan, D.S.H. 
Leang, S.E.
Issue Date: 1999
Source: Kok, C.K.,Chew, W.C.,Chim, W.K.,Chan, D.S.H.,Leang, S.E. (1999). Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements. Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA : 200-205. ScholarBank@NUS Repository.
Abstract: Extracted charge profiles of lightly-doped drain (LDD) surface-channel and buried-channel pMOS devices stressed under hot-carrier injection conditions reveal predominant electron trapping near the gate edge at the drain region in both cases. From threshold voltage measurements, there is some evidence of hole trapping after long stress times in surface-channel pMOSFETs, but not in buried-channel devices. Hot-electron trapping is the dominant degradation mechanism in buried-channel LDD pMOSFETs. For surface-channel LDD pMOSFETs, large concentrations of electron traps near the gate edge were found.
Source Title: Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
URI: http://scholarbank.nus.edu.sg/handle/10635/72523
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

Page view(s)

29
checked on Dec 9, 2017

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.