An accurate delay model for BiCMOS logic gates

Abstract

An accurate delay model for BiCMOS logic gates is presented. To meet the requirements of modern technologies in submicron regions, using the Nth-power MOS model, an analytical BiCMOS delay model is developed directly based on the BiCMOS inverter driving the RC load. A fairly good match between the new delay model and SPICE simulation waveforms is observed. This new BiCMOS delay model is also extended to complex logic gates, such as NAND and NOR gates by considering the series-connected MOS structures, which is the key feature for system analysis and gate optimization. The input slope effect is also included in this new delay model. The calculated results of the new delay model and SPICE simulation are compared under different conditions such as different RC load, different series-connected gates, and a good match is observed.