Please use this identifier to cite or link to this item: https://doi.org/10.1109/IECON.2004.1433364
Title: Optimal power converter topology for powering future microprocessor demands
Authors: Singh, R.P.
Khambadkone, A.M. 
Samudra, G.S. 
Liang, Y.C. 
Issue Date: 2004
Source: Singh, R.P.,Khambadkone, A.M.,Samudra, G.S.,Liang, Y.C. (2004). Optimal power converter topology for powering future microprocessor demands. IECON Proceedings (Industrial Electronics Conference) 1 : 530-535. ScholarBank@NUS Repository. https://doi.org/10.1109/IECON.2004.1433364
Abstract: Higher computation speeds demand higher clock frequencies, which means increased power loss. To decrease the power loss, it becomes necessary to reduce the operating voltage. Hence the future microprocessors will operate at significantly lower voltages and demand much higher currents than the present generation microprocessors. They require voltage regulating modules (VRM) to provide the desired regulated power supply. In addition, due to increased clock frequencies and higher currents, these microprocessors will present high slew rates during transient. To meet these demands, we need to have high power density, heavier load and tight voltage regulating modules having high efficiency over a wide range of load and having good transient response. In this paper, we present the requirements for the VRMs for future microprocessors and discuss the limitations of the existing topologies. © 2004 IEEE.
Source Title: IECON Proceedings (Industrial Electronics Conference)
URI: http://scholarbank.nus.edu.sg/handle/10635/71293
DOI: 10.1109/IECON.2004.1433364
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