M-V MOSFETs: Surface passivation, source/drain and channel strain engineering, self-aligned contact metallization

Abstract

In this paper, we discuss the research and development of gate-stack, source/drain, and contact process modules for high-mobility III-V n-MOSFETs. Work performed in our research group will be reviewed. Surface passivation technologies were developed for forming gate stacks on III-V materials such as GaAs and InGaAs. In situ doped lattice-mismatched source/drain (S/D) stressors were integrated in InGaAs MOSFETs with for reduction of S/D series resistance as well as for channel strain engineering. High-stress liner stressor was also used for inducing strain in the channel of InGaAs FETs. Several salicide-like process technologies were developed for self-aligned contact metallization in III-V MOSFETs. A III-V multiple-gate transistor with lightly doped fin with retrograde doping for suppression of short channel effects was demonstrated.