Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/71007
Title: Modelling, analysis and design of cascaded forward and interleaved converter for powering future microprocessors
Authors: Singh, R.P.
Khambadkone, A.M. 
Samudra, G.S. 
Liang, Y.C. 
Keywords: Forward converter
Interleaved converter
Terms-DC-DC converter
Two-stage
Voltage regulating module (VRM)
Issue Date: 2005
Source: Singh, R.P.,Khambadkone, A.M.,Samudra, G.S.,Liang, Y.C. (2005). Modelling, analysis and design of cascaded forward and interleaved converter for powering future microprocessors. Proceedings of the International Conference on Power Electronics and Drive Systems 1 : 430-435. ScholarBank@NUS Repository.
Abstract: The future microprocessors will operate at significantly lower voltages and demand much higher currents than the present generation microprocessors. They require voltage regulating modules (VRM) to provide the desired regulated power supply. In this paper, we present the requirements for the VRMs for future microprocessors and discuss the limitations of the existing topologies. Due to narrow duty ratio of single stage conversion, there is non-uniform distribution of losses. Thus a two-stage conversion comprising of an isolated stage as the front end and a phase-shifted interleaved converter as the backend is discussed. A small-signal model is derived for an interleaved converter, taking into account the asymmetry in the circuit elements. Finally a controller is designed for a cascaded system. © 2005 IEEE.
Source Title: Proceedings of the International Conference on Power Electronics and Drive Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/71007
ISBN: 0780392965
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