Please use this identifier to cite or link to this item: https://doi.org/10.1109/ReCoSoC.2012.6322894
Title: Fault-tolerant network interface for spatial division multiplexing based network-on-chip
Authors: Das, A.
Kumar, A. 
Veeravalli, B. 
Keywords: Fault-Tolerance
Network Interface
Network-on-Chip
Spatial Division Multiplexing
Issue Date: 2012
Source: Das, A.,Kumar, A.,Veeravalli, B. (2012). Fault-tolerant network interface for spatial division multiplexing based network-on-chip. ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings : -. ScholarBank@NUS Repository. https://doi.org/10.1109/ReCoSoC.2012.6322894
Abstract: The progressive maturity of VLSI manufacturing technology is helping in integrating more and more processing elements and memory units on a single die to form a Multiprocessor System-On-Chip (MPSoC). Network-on-Chip (NoC) is adopted as communication backbone for most of these modern day multiprocessor systems. As complexity of these system scales, there has been a growing concern on the dependability of these processing and communication elements. In this paper, we propose a centralized hardware fault-tolerant network interface (NI) for NoCs based on spatial division multiplexing. Experiments show that the proposed design has better throughput than a non fault-tolerant design with only 18% area overhead. We also introduce an area optimized distributed fault-tolerant NI architecture which provides 50% more throughput than the centralized design for high fault rates. © 2012 IEEE.
Source Title: ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings
URI: http://scholarbank.nus.edu.sg/handle/10635/70319
ISBN: 9781467325721
DOI: 10.1109/ReCoSoC.2012.6322894
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