Please use this identifier to cite or link to this item:
|Title:||Fast and accurate interval-based timing estimator for variability-aware FPGA physical synthesis tools|
|Source:||Lee, C.S., Loke, W.T., Zhang, W., Ha, Y. (2007). Fast and accurate interval-based timing estimator for variability-aware FPGA physical synthesis tools. Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL : 279-284. ScholarBank@NUS Repository. https://doi.org/10.1109/FPL.2007.4380660|
|Abstract:||Process variations of deep sub-micron technologies have created significant timing uncertainty. This generates the need for a new variability-aware physical synthesis tool for Field-Programmable Gate-Arrays (FPGAs). Ideally, variability-aware tools should be able to perform both timing variability estimation during the synthesis and timing variability analysis after the synthesis. Statistical static timing analysis (SSTA) methods are developed to perform timing variability analysis, but are computationally expensive and not fast enough. We propose a fast and accurate interval-based method for the timing variability estimation. This method uses correlation-aware affine intervals instead of probability density distributions to model timing uncertainties. Our model estimates the mean of timing variation within an accuracy of 99.9% and an average range looseness of -7.5% for the Monte Carlo (MC) model. A speed-up of about 80X and 4900X is achieved for the Correlation Aware Canonical Timing (CACT) model and MC model respectively. © 2007 IEEE.|
|Source Title:||Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Feb 22, 2018
checked on Feb 19, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.