Please use this identifier to cite or link to this item: https://doi.org/10.1109/TVLSI.2005.857177
Title: Equivalent circuit model of on-wafer CMOS interconnects for RFICs
Authors: Shi, X.
Ma, J.-G.
Yeo, K.S.
Do, M.A.
Li, E. 
Keywords: Empirical formulas
Lumped equivalent circuit model
Modeling
RF CMOS interconnects
Scalable
Scattering parameters measurement
Skin effect
Substrate losses
Issue Date: Sep-2005
Source: Shi, X., Ma, J.-G., Yeo, K.S., Do, M.A., Li, E. (2005-09). Equivalent circuit model of on-wafer CMOS interconnects for RFICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (9) : 1069-1071. ScholarBank@NUS Repository. https://doi.org/10.1109/TVLSI.2005.857177
Abstract: This paper investigates the properties of the on-wafer interconnects built in a 0.18-μm CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated. © 2005 IEEE.
Source Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/70195
ISSN: 10638210
DOI: 10.1109/TVLSI.2005.857177
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