Design and implementation of multiple addresses parallel transmission architecture for storage area network

Abstract

In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows between multiple devices can be balanced in an asymmetrical topology without using special hardware. The SAN performance could be scaled flexibly and additional fault tolerance feature is provided. The load balancing algorithms we provide can be easily implemented and the computation is efficient enough for high-speed transmission.