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|Title:||Codes reallocation and prediction for power efficiency in I-cache memory|
|Citation:||Zhu, X.,Tay, T.T. (2005). Codes reallocation and prediction for power efficiency in I-cache memory. ASICON 2005: 2005 6th International Conference on ASIC, Proceedings 1 : 164-167. ScholarBank@NUS Repository.|
|Abstract:||To reduce energy consumption of cache memories is an important problem since this component spends a large portion of energy in a microprocessor. This paper proposes a compiler predicted strategy that dynamically turns off those unused cache lines to save power in architecture level. In our algorithm, the object codes of programs are re allocated in memory address map according to the I-cache structure so that the working sets are reduced in the cache memory. In addition, a few special cache-scaling instructions (CSIs) are added to the object codes to track the working set size. With the information from CSIs and the current system state, a hardware controller implements the decision of replacement algorithm and switching the power of each refill-line. Our experimental results indicate that the compiler-predicted algorithm can reduce 58.9% of energy in a 32K I-cache, while the average performance loss is only 2.7%. © 2005 IEEE.|
|Source Title:||ASICON 2005: 2005 6th International Conference on ASIC, Proceedings|
|Appears in Collections:||Staff Publications|
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