Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/68722
Title: A branch target instruction prefetchnig technique for improved performance
Authors: Gade, P.R.
Paily, R.
Ha, Y. 
Issue Date: 2007
Citation: Gade, P.R.,Paily, R.,Ha, Y. (2007). A branch target instruction prefetchnig technique for improved performance. Proceedings of the 15th International Conference on Advanced Computing and Communications, ADCOM 2007 : 345-350. ScholarBank@NUS Repository.
Abstract: Modern processors are much faster than the main memory. Cache memories are introduced to reduce this speed gap. However, instruction cache misses can severely limit the performance of today's superscalar processors. Prefetch algorithms attempt to reduce the performance degradation by bringing cache lines into the instruction cache. Different algorithms like next line, target line and wrong-path prefetching are well studied. A new Branch Target Address (BTA) prefetching scheme is proposed. This technique substantially reduces the cycles loss due to branch instruction cache misses. It has achieved substantial performance improvement over other prefetching techniques; for example 10-15% improvement over wrong-path instruction prefetching. With the help of a small size additional buffer, cache access rate as well as cache pollution has been reduced drastically. The new scheme works better in processor designs where memory latencies are likely to be longer. © 2007 IEEE.
Source Title: Proceedings of the 15th International Conference on Advanced Computing and Communications, ADCOM 2007
URI: http://scholarbank.nus.edu.sg/handle/10635/68722
ISBN: 0769530591
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

Page view(s)

38
checked on Jun 22, 2018

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.