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Title: Vertical silicon nanowire platform for low power electronics and clean energy applications
Authors: Lo, G.Q.
Kwong, D.-L.
Li, X.
Sun, Y.
Ramanathan, G.
Chen, Z.X.
Wong, S.M.
Li, Y.
Shen, N.S.
Buddharaju, K.
Yu, Y.H.
Lee, S.J. 
Singh, N.
Issue Date: 2012
Source: Lo, G.Q.,Kwong, D.-L.,Li, X.,Sun, Y.,Ramanathan, G.,Chen, Z.X.,Wong, S.M.,Li, Y.,Shen, N.S.,Buddharaju, K.,Yu, Y.H.,Lee, S.J.,Singh, N. (2012). Vertical silicon nanowire platform for low power electronics and clean energy applications. Journal of Nanotechnology : -. ScholarBank@NUS Repository.
Abstract: This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.
Source Title: Journal of Nanotechnology
ISSN: 16879503
DOI: 2012/492121
Appears in Collections:Staff Publications

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