Efficient height reduction over-the-cell channel router

Abstract

The authors present a new algorithm for both two-layer and three-layer over-the-cell channel routing in the standard cell VLSI design. The approach exploits vacant terminals on the channel boundary effectively. It considers the following factors simultaneously to select net segments for routing over the cells: density distribution in the channel, the longest path in the vertical constraint graph, elimination of cycles in the vertical constraint graph and reduction in maximum cliques in the horizontal constraint graph. With respect to the PRIMARY 1 benchmark examples, the router achieved a 41.3% improvement over the Greedy channel router (one Without using over-the-cell area) for a two-layer routing model and a 61.0% improvement for a three-layer routing model. This outperforms all previous algorithms.