Determination of LDD MOSFET drain resistance from device simulation

Abstract

A simple, efficient and accurate technique for the determination of the drain resistance of LDD MOSFETs, using a two-dimensional device simulator, is presented. This method does not require the artificial introduction of constraints that would alter the normal operating conditions and geometry of the device. Comparison is made with a more elaborate technique, where the drain region is modelled as a network of resistances. For an appropriately chosen mesh size, good agreement to within 10% has been achieved for the two techniques. In terms of computational labour, the simple technique enjoys at least an order of magnitude advantage compared with the more elaborate model. The two techniques have also been used to study the dependence of the drain resistance on the gate and the drain bias, and to establish the accuracy over a broad bias range. An estimate is also made of the degradation of the drain resistance due to hot-carrier stress.