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|Title:||Planar microspring - A novel compliant chip-to-package interconnect for wafer-level packaging|
Planar microspring interconnect
|Citation:||Liao, E.B., Tay, A.A.O., Ang, S.S.T., Feng, H.H., Nagarajan, R., Kripesh, V., Kumar, R., Lo, G.Q. (2009). Planar microspring - A novel compliant chip-to-package interconnect for wafer-level packaging. IEEE Transactions on Advanced Packaging 32 (2) : 379-389. ScholarBank@NUS Repository. https://doi.org/10.1109/TADVP.2008.924247|
|Abstract:||In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a J-shaped spring design produces a combination of high 3-D compliances and acceptable electrical parasitics. Further, numerical analyses on the J-shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 μm). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to ∼ 35 GHz without significant power loss. © 2009 IEEE.|
|Source Title:||IEEE Transactions on Advanced Packaging|
|Appears in Collections:||Staff Publications|
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