Please use this identifier to cite or link to this item: https://doi.org/10.1016/S0378-4754(01)00329-9
Title: Large matrix-vector products on distributed bus networks with communication delays using the divisible load paradigm: Performance analysis and simulation
Authors: Chan, S.K.
Bharadwaj, V. 
Ghose, D.
Keywords: Bus networks
Communication delay
Computation delay
Divisible load
Matrix-vector product
Processing time minimisation
Issue Date: 2001
Source: Chan, S.K.,Bharadwaj, V.,Ghose, D. (2001). Large matrix-vector products on distributed bus networks with communication delays using the divisible load paradigm: Performance analysis and simulation. Mathematics and Computers in Simulation 58 (1) : 71-92. ScholarBank@NUS Repository. https://doi.org/10.1016/S0378-4754(01)00329-9
Abstract: We present a performance analysis and experimental simulation results on the problem of scheduling a divisible load on a bus network. In general, the computing requirement of a divisible load is CPU intensive and demands multiple processing nodes for efficient processing. We consider the problem of scheduling a very large matrix-vector product computation on a bus network consisting of a homogeneous set of processors. The experiment was conducted on a PC-based networking environment consisting of Pentium II machines arranged in a bus topology. We present a theoretical analysis and verify these findings on the experimental test-bed. We also developed a software support system with flexibility in terms of scalability of the network and the load size. We present a detailed discussion on the experimental results providing directions for possible future extensions of this work. © 2001 IMACS. Published by Elsevier Science B.V. All rights reserved.
Source Title: Mathematics and Computers in Simulation
URI: http://scholarbank.nus.edu.sg/handle/10635/56452
ISSN: 03784754
DOI: 10.1016/S0378-4754(01)00329-9
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