Please use this identifier to cite or link to this item: https://doi.org/10.1109/16.974729
Title: Folded gate LDMOS transistor with low on-resistance and high transconductance
Authors: Zhu, Y.
Liang, Y.C. 
Xu, S.
Foo, P.-D.
Sin, J.K.O.
Keywords: Folded gate
LDMOS
Power IC
UMOS
Issue Date: Dec-2001
Source: Zhu, Y., Liang, Y.C., Xu, S., Foo, P.-D., Sin, J.K.O. (2001-12). Folded gate LDMOS transistor with low on-resistance and high transconductance. IEEE Transactions on Electron Devices 48 (12) : 2917-2928. ScholarBank@NUS Repository. https://doi.org/10.1109/16.974729
Abstract: In this paper, a novel folded gate LDMOS transistor (FG-LDMOST) structure is proposed with the properties of low on-resistance and high transconductance. The FG structure is formed by adding a single trench process into the conventional LDMOS process. In this way, the channel density can be largely increased after the additional process. From the data by laboratory measurement, with the FG concept applied, the specific on-resistance of FG-LDMOS device is reduced by 45.66% compared to the conventional LDMOS structure with similar dimensions. At the same time, the transconductance value is improved by 64.09%. The capacitance anal effective channel mobility for both FG-LDMOST and the counterpart are also measured anal compared. The significance of the FG concept can also be applied in making CMOS and other MOS-gated devices in low to medium operating voltage ranges.
Source Title: IEEE Transactions on Electron Devices
URI: http://scholarbank.nus.edu.sg/handle/10635/56078
ISSN: 00189383
DOI: 10.1109/16.974729
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