Please use this identifier to cite or link to this item: https://doi.org/10.1109/ICCD.2009.5413145
Title: The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies
Authors: Koh, C.-K.
Wong, W.-F. 
Chen, Y.
Li, H.
Issue Date: 2009
Source: Koh, C.-K., Wong, W.-F., Chen, Y., Li, H. (2009). The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors : 268-274. ScholarBank@NUS Repository. https://doi.org/10.1109/ICCD.2009.5413145
Abstract: There has been much work on the next generation of memory technologies such as MRAM, RRAM and PRAM. Most of these are non-volatile in nature, and compared to SRAM, they are often denser, just as fast, and have much lower energy consumption. Using 3-D stacking technology, it has been proposed that they can be used instead of SRAM in large level 2 caches prevalent in today's microprocessors. However, one of the key challenges in the use of these technologies, such as MRAM, is their higher fault probabilities arising from the larger process variation, defects in its fabrication, and the fact that the cache is much larger. This seriously affect yield. In this paper, we propose a fault resilient set associative cache architecture which we called the salvage cache. In the salvage cache, a faulty cache block is sacrificed and used to repair faults found in other blocks. We will describe in detail the architecture of the salvage cache as well as provide results of yield simulations that show that a much higher yield can be achieved viz-a-viz other fault tolerant techniques. We will also show the performance savings that arise from the use of a large next-generation L2 cache. ©2009 IEEE.
Source Title: Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
URI: http://scholarbank.nus.edu.sg/handle/10635/42185
ISBN: 9781424450282
ISSN: 10636404
DOI: 10.1109/ICCD.2009.5413145
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