Please use this identifier to cite or link to this item:
|Title:||Interprocedural placement-aware configuration prefetching for FPGA-based systems|
|Authors:||Sim, J.E. |
|Source:||Sim, J.E., Wong, W.-F., Walla, G., Ziermann, T., Teich, J. (2010). Interprocedural placement-aware configuration prefetching for FPGA-based systems. Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010 : 179-182. ScholarBank@NUS Repository. https://doi.org/10.1109/FCCM.2010.35|
|Abstract:||One of the major impediments to deploying partially run-time reconfigurable FPGAs as hardware accelerators is the time overhead involved in loading the hardware modules. While configuration prefetching is an effective method that can be employed to reduce this overhead, mispredicted prefetches may worsen the situation by increasing the number of reconfigurations needed. In this paper, we present a static algorithm for configuration prefetching in partially reconfigurable FPGAs that minimizes the reconfiguration overhead. By making use of profiling, the interprocedural control flow graph, and the placement information of hardware modules, our algorithm predicts hardware execution and tries to prefetch hardware modules as early as possible while minimizing the risk of mis-predictions. Our experiments show that our algorithm performs significantly better than current-state-of-the- art prefetching algorthms for control-bound applications. © 2010 IEEE.|
|Source Title:||Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Dec 14, 2017
WEB OF SCIENCETM
checked on Nov 20, 2017
checked on Dec 10, 2017
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.