Please use this identifier to cite or link to this item: https://doi.org/10.1109/FPL.2007.4380659
Title: Disjoint pattern enumeration for custom instructions identification
Authors: Yu, P.
Mitra, T. 
Keywords: ASIPs
Custom instruction
Customizable processors
Instruction-set extensions
Subgraph enumeration algorithm
Issue Date: 2007
Source: Yu, P., Mitra, T. (2007). Disjoint pattern enumeration for custom instructions identification. Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL : 273-278. ScholarBank@NUS Repository. https://doi.org/10.1109/FPL.2007.4380659
Abstract: Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analysis of the program's dataflow graphs. The characteristics of certain applications and the modern compiler optimization techniques (e.g., loop unrolling, region formation, etc.) have lead to substantially larger dataflow graphs. Hence, it is computationally expensive to automatically select the optimal set of custom instructions. Heuristic techniques are often employed to quickly search the design space. In order to leverage full potential of custom instructions, our previous work proposed an efficient algorithm for exact enumeration of all possible candidate instructions (or patterns) given the dataflow graphs. But the algorithm was restricted to connected computation patterns. In this paper, we describe an efficient algorithm to generate all feasible disjoint patterns starting with the set of feasible connected patterns. Compared to the state-of-the-art technique, our algorithm achieves orders of magnitude speedup while generating the identical set of candidate disjoint patterns. © 2007 IEEE.
Source Title: Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
URI: http://scholarbank.nus.edu.sg/handle/10635/41933
ISBN: 1424410606
DOI: 10.1109/FPL.2007.4380659
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