Please use this identifier to cite or link to this item: https://doi.org/10.1145/2228360.2228434
Title: WCET-centric partial instruction cache locking
Authors: Ding, H.
Liang, Y.
Mitra, T. 
Keywords: partial cache locking
WCET
Issue Date: 2012
Source: Ding, H.,Liang, Y.,Mitra, T. (2012). WCET-centric partial instruction cache locking. Proceedings - Design Automation Conference : 412-420. ScholarBank@NUS Repository. https://doi.org/10.1145/2228360.2228434
Abstract: Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in Worst-case Execution Time (WCET) estimation due to unpredictable access latencies. Modern embedded processors often include cache locking mechanism for better timing predictability. As the cache contents are statically known, memory access latencies are predictable, leading to precise WCET estimate. Moreover, by carefully selecting the memory blocks to be locked, WCET estimate can be reduced compared to cache modeling without locking. Existing static instruction cache locking techniques strive to lock the entire cache to minimize the WCET. We observe that such aggressive locking mechanisms may have negative impact on the overall WCET as some memory blocks with predictable access behavior get excluded from the cache. We introduce a partial cache locking mechanism that has the flexibility to lock only a fraction of the cache. We judiciously select the memory blocks for locking through accurate cache modeling that determines the impact of the decision on the program WCET. Our synergistic cache modeling and locking mechanism achieves substantial reduction in WCET for a large number of embedded benchmark applications. © 2012 ACM.
Source Title: Proceedings - Design Automation Conference
URI: http://scholarbank.nus.edu.sg/handle/10635/41756
ISBN: 9781450311991
ISSN: 0738100X
DOI: 10.1145/2228360.2228434
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