Please use this identifier to cite or link to this item: https://doi.org/10.1109/RTAS.2011.27
Title: Scope-aware data cache analysis for WCET estimation
Authors: Huynh, B.K. 
Ju, L.
Roychoudhury, A. 
Keywords: abstract interpretation
cache memories
data cache behavior prediction
program analysis
real-time applications
worst case execution time
Issue Date: 2011
Source: Huynh, B.K., Ju, L., Roychoudhury, A. (2011). Scope-aware data cache analysis for WCET estimation. Real-Time Technology and Applications - Proceedings : 203-212. ScholarBank@NUS Repository. https://doi.org/10.1109/RTAS.2011.27
Abstract: Caches are widely used in modern computer systems to bridge the increasing gap between processor speed and memory access time. On the other hand, presence of caches, especially data caches, complicates the static worst case execution time (WCET) analysis. Access pattern analysis (e.g., cache miss equations) are applicable to only a specific class of programs, where all array accesses must have predictable access patterns. Abstract interpretation-based methods (must/persistence analysis) determines possible cache conflicts based on coarse-grained memory access information from address analysis, which usually leads to significantly pessimistic estimation. In this paper, we first present a refined persistence analysis method which fixes the potential underestimation problem in the original persistence analysis. Based on our new persistence analysis, we propose a framework to combine access pattern analysis and abstract interpretation for accurate data cache analysis. We capture the dynamic behavior of a memory access by computing its temporal scope (the loop iterations where a given memory block is accessed for a given data reference) during address analysis. Temporal scopes as well as loop hierarchy structure (the static scopes) are integrated and utilized to achieve a more precise abstract cache state modeling. Experimental results shows that our proposed analysis obtains up to 74% reduction in the WCET estimates compared to existing data cache analysis. © 2011 IEEE.
Source Title: Real-Time Technology and Applications - Proceedings
URI: http://scholarbank.nus.edu.sg/handle/10635/41073
ISBN: 9780769543444
ISSN: 10801812
DOI: 10.1109/RTAS.2011.27
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