Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/40800
Title: Scalable custom instructions identification for instruction-set extensible processors
Authors: Yu, P.
Mitra, T. 
Keywords: ASIPs
Customizable processors
Instruction-set extensions
Subgraph enumeration algorithm
Issue Date: 2004
Source: Yu, P.,Mitra, T. (2004). Scalable custom instructions identification for instruction-set extensible processors. CASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems : 69-78. ScholarBank@NUS Repository.
Abstract: Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. However, it is computationally expensive to automatically select the optimal set of custom instructions. Therefore, heuristic techniques are often employed to quickly search the design space. In this paper, we present an efficient algorithm for exact enumeration of all possible candidate instructions given the dataflow graph (DFG) corresponding to a code fragment. Even though this is similar to the "subgraph enumeration" problem (which is exponential), we find that most subgraphs are not feasible candidates for various reasons. In fact, the number of candidates is quite small compared to the size of the DFG. Compared to previous approaches, our technique achieves orders of magnitude speedup in enumerating these candidate custom instructions for very large DFGs. Copyright 2004 ACM.
Source Title: CASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/40800
ISBN: 1581138903
Appears in Collections:Staff Publications

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