Please use this identifier to cite or link to this item: https://doi.org/10.1109/ICCAD.2008.4681641
Title: Temperature aware task sequencing and voltage scaling
Authors: Jayaseelan, R.
Mitra, T. 
Issue Date: 2008
Source: Jayaseelan, R.,Mitra, T. (2008). Temperature aware task sequencing and voltage scaling. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD : 618-623. ScholarBank@NUS Repository. https://doi.org/10.1109/ICCAD.2008.4681641
Abstract: On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of system design. In this paper, we propose task sequencing as a powerful and complimentary mechanism to voltage scaling in improving the thermal profile of an embedded system executing a set of periodic heterogenous tasks under timing constraints. We first derive the peak temperature of a repeating task sequence analytically and develop a heuristic to construct the task sequence that minimizes the peak temperature. Experimental evaluation shows that our task sequencing heuristic achieves peak temperature within 0.5°C of the optimal solution and 7.47°C lower, on an average, compared to the worst sequence for a large range of embedded task sets. We also propose an iterative algorithm that combines task sequencing with voltage scaling to further lower the peak temperature while satisfying the timing constraints. For embedded task sets, our combined task sequencing and voltage scaling approach achieves, on an average, 2.1°C-6.94°C reduction in peak temperature compared to voltage scaling alone.
Source Title: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
URI: http://scholarbank.nus.edu.sg/handle/10635/40798
ISBN: 9781424428205
ISSN: 10923152
DOI: 10.1109/ICCAD.2008.4681641
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