Please use this identifier to cite or link to this item: https://doi.org/10.1109/ICCD.2007.4601944
Title: VOSCH: Voltage scaled cache hierarchies
Authors: Wong, W.-F. 
Kon, C.-K.
Chen, Y.
Li, H.
Issue Date: 2007
Source: Wong, W.-F., Kon, C.-K., Chen, Y., Li, H. (2007). VOSCH: Voltage scaled cache hierarchies. 2007 IEEE International Conference on Computer Design, ICCD 2007 : 496-503. ScholarBank@NUS Repository. https://doi.org/10.1109/ICCD.2007.4601944
Abstract: The cache hierarchy of state-of-the-art - especially multicore - microprocessors consumes a significant amount of area and energy. A significant amount of research has been devoted especially to reducing the latter. One of the most important microarchitectural techniques proposed for the energy management is dynamic voltage scaling (DVS). In DVS solutions, each cache operates at a number of different voltages. Most of the research in DVS techniques have been around how the voltages can be adjusted and tuned. In this paper, we depart from the use of DVS for energy conservation by examining static voltage assignments for caches. We propose the use of voltage scaled cache hierarchies (VOSCH) as a means to conserve both static and dynamic energy. In VOSCH, the caches are powered at progressively lower supply voltages as the cache level increases. Compared to DVS solutions, VOSCH is simple, potentially more robust and can conserve more energy. We also experimented with more aggressive designs that included the addition of small cache structures to VOSCH. Even greater energy savings were achieved without having to sacrifice performance. © 2007 IEEE.
Source Title: 2007 IEEE International Conference on Computer Design, ICCD 2007
URI: http://scholarbank.nus.edu.sg/handle/10635/40005
ISBN: 1424412587
DOI: 10.1109/ICCD.2007.4601944
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